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Heterogeneous 3D Integrated Circuits – Current Problems

May 7 @ 2:00 pm - 3:00 pm

As the sizing of transistors comes to the atomic distance limitations further development becomes possible by either introduction of new technologies or changing in geormetric arrangements of the elements and building blocks. Limitations in microcircuit constructions can be avoided by putting whole building blocks and sub-circuits in 3-dimensional stacks. Such an approach allows for efficient space usage at the same time allowing circuit footprint reduction. Also routing solutions offer very significant wire-length reductions thus reducing power dissipations and signal delays. 3D integration looks as a fantastic area of development, however, there are many new challenges and problems to be solved. 3D integration offers also unprecedented opportunities by allowing blocks fabricated in heterogeneous technologies to be integrated in one chip. This allows for integration of microprocessors, memories, RF circuitry, sensors, batteries and hyper-capacitors, energy harvesting blocks, biological and chemical sensors and many new types of building blocks in one chip. Current state and new perspectives are discussed.

Speaker(s): Maciej Ogorzalek,

Location:
Room: ASB 10940 (SFU’s Big Data Visualization Lab)
Bldg: Applied Sciences Building
Simon Fraser University
8888 University Drive
Burnaby, British Columbia
V5A 1S6

Details

Date:
May 7
Time:
2:00 pm - 3:00 pm
Website:
More Information and Registration

Organizer

ljilja@cs.sfu.ca