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Physical Design Automation of Transistor Networks

May 7 @ 3:30 pm - 4:30 pm

A way to reduce power consumption is to reduce the number of transistors used to implement a circuit, as leakage power is proportional to the number of transistors. It is shown a physical design approach to reduce the number of transistors needed to perform a task. It is proposed an EDA tool set to automatically generate the physical design of any transistor network. It shows an important reduction on power, improving also reliability. A standard cell library has a limited number of logical functions, and a limited number of sizings. The talk is target in optimization methods to reduce the number of transistors of a circuit. The methods allow the realization of any possible logical function or transistor network. It is included comparisons with solutions using the traditional standard cell methodology.

Speaker(s): Ricardo Reis,

Location:
Room: ASB 10940 (SFU’s Big Data Visualization Lab)
Bldg: Applied Sciences Building
Simon Fraser University
8888 University Drive
Burnaby, British Columbia
V5A 1S6

Details

Date:
May 7
Time:
3:30 pm - 4:30 pm
Website:
More Information and Registration

Organizer

ljilja@cs.sfu.ca