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Cryogenic CMOS for low power quantum computing applications: Roadmap, present status, challenges and opportunities

June 6 @ 4:00 pm - 5:30 pm

Distinguished Lecturer technical seminar with the following abstract: This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from a roadmap level understanding and future trends, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10^-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW. Co-sponsored by: CH07098 – Vancouver/Victoria Sect Jt Chapter, CAS04 Speaker(s): Sudipto Chakraborty, Room: MCLD 3038, Bldg: MacLeod Building , 2356 Main Mall, Vancouver, British Columbia, Canada, V6T 1Z4, Virtual: https://events.vtools.ieee.org/m/363109