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IEEE EDS Distinguished Lecturer Talk: “Noise Performance challenges for MOS devices at nanoscale”
November 2 @ 2:00 pm - 3:00 pm
Abstract: After the first demonstration of the MOSFET in 1960 at Bell Laboratories, the understanding of its intrinsic noise mechanisms quickly followed. However, poor sensitivity of integrated lightwave receivers could not be explained based on the above analyses. To understand and push these limits of the then nascent MOS technology, discovery and understanding of a host of extrinsic noise mechanisms was actively pursued at Bell Labs. In this presentation, a physical understanding of both intrinsic and extrinsic noise mechanisms in an IGFET is developed. Intrinsic noise mechanisms fundamental to device operation include channel thermal noise, induced gate noise and induced substrate noise. Non-quasi-static effects that have been analytically modeled are also discussed. Extrinsic noise mechanisms manifested due to structural evolution of the MOSFET include excess channel noise, distributed gate resistance noise, distributed substrate resistance noise, bulk charge effects, substrate current super-shot noise and gate current noise. Changes in the device structure to improve the noise performance by suppressing the effects of the extrinsic noise mechanisms will also be discussed. This work has resulted in almost an order of magnitude improvement in the noise performance of these devices making them an ideal choice for wireless and lightwave communications. MOSFET excess channel noise continues to be an active area of research. Speaker(s): Renuka, Room: ASB 10704, Bldg: Applied Science Building, 8888 University Dr., Burnaby, British Columbia, Canada, V5A 1S6, Virtual: https://events.vtools.ieee.org/m/371969