CMOS scaling maintains economic relevance with 5nm SoCs already in high-volume production for 2.5 years and 3nm well into risk production. Modest feature size reduction and design/technology innovations co-optimized primarily for logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we start with a brief history of transistor evolution to motivate the migration from planar Dennard-era transistors to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges impacting design. To address the growing effort required for physical design closure, we cover design strategies including density-friendly layout, continuous active area layout, and template-based analog cells. We conclude with a discussion of what remains in finFET development and a peek at transistor architectures on the horizon. Speaker(s): Alvin Loke, Bldg: MacLeod Building , MCLD 3038, 2356 Main Mall, Vancouver, British Columbia, Canada, V6T 1Z4