Technical Seminar by Dr. Ramin Farjadrad with the following abstract: For the past 4 decades, industry has supported 2x conpute performance increase every 2 years, a trend supported by Moore’s Law. However, not only has Moore’s law come to an end, but also the exponential demand for more AI/HPC had driven the performance demand close to 10x/year. This recent trend has resulted in the chips growing significantly in size, to include more compute cores, exceeding maximum chip manufacturing dimensions. The chiplet system-in-package (SiP) enables implementing very large processor chips by connecting several smaller chiplets. These chiplets must be connected at very high bandwidth and low power, to perform like a single chip. Advanced packaging technologies like silicon interposers are developed to connect chiplets at the target bandwidths/powers. However, advanced packaging solutions, besides being super expensive, come with many limitations. A major limitation is their supply chain. Currently, TSMC is the sole provider of large Silicon Interposers that are critical for AI/HPC chips. Even without any geopolitical risk that may limit TSMC’s suppl, TSMC cannot deliver the worldwide interposer demand in near future. This presentation introduces novel chiplet connectivity technologies that enables creating high-end AI/HPC chips without the need for large interposers. Speaker(s): , Ramin Farjadrad Vancouver, British Columbia, Canada, Virtual: https://events.vtools.ieee.org/m/379704