By the end of years 70s, microprocessors were designed by hand showing excellent layout compaction. It will be shown some highlights of the reverse engineering of the Z8000, which control part was designed by hand, showing several layout optimization strategies. The observation of the Z8000 layout inspired the research of methods to do the automatic generation of the layout of any transistor network, allowing to reduce the number of transistors to implement a circuit, and by consequence, the leakage power. Some of the layout automation tools developed by our group are briefly presented. Speaker(s): Ricardo Reis, Room: TBA, Bldg: Applied Science Building , Simon Fraser University, Burnaby , British Columbia, Canada, V5A 1S6, Virtual: https://events.vtools.ieee.org/m/561894